问题[vhdl](coding)

下面的代码产生-

错误（10327）：XXXX.vhd(1581) 处的 VHDL 错误：无法确定运算符“＆”的定义 - 找到 47 个可能的定义错误（10647）：XXXX.vhd(1581) 处的 VHDL 类型推断错误：表达式类型不明确 - “std_logic_vector”或“slvn_array”是两种可能的匹配错误（10411）：XXXX.vhd(1581) 处的 VHDL 类型转换错误：无法确定文本或符号“UNSIGNED”附近的对象或表达式的类型

----CODE
usb_hid_phy_offload_address         <= std_logic_vector(unsigned(ENDPOINT0_CTRL_REG) + unsigned((("00000") & (cfg_hid_ep(v_selp)(5 downto 0)) & ("00"))));
---END CODE

我已经尝试了所有能想到的组合。欢迎提出任何建议。

constant g_num_usbs  : integer range 1 to 8 := 2 ;
type     slvn_array is array (natural range <>) of  std_logic_vector ;

signal usb_hid_phy_offload_address : std_logic_vector(12 downto 0) ;
constant ENDPOINT0_CTRL_REG        : std_logic_vector(12 downto 0) := '0' & x"040" ;
signal cfg_hid_ep : slvn_array(g_num_usbs-1 downto 0)( 7 downto 0)  ;

Questa 出现此错误（在 EDA Playground 上使用 -2008 进行编译）

-- Compiling architecture rtl of foo
** Error: design.vhd(31): Type error resolving infix expression "xnor" as type ieee.NUMERIC_STD.UNSIGNED.
** Note: design.vhd(31): (vcom-1499) Aggregate with a single element association must use named association.

对于此示例代码

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
  port(
 clk  : in std_logic;
 reset: in std_logic;
 din  : in std_logic;
 dout: out unsigned(7 downto 0)
      );
end entity foo;

architecture rtl of foo is

signal prbs_fb  : unsigned(0 downto 0);
-- changing to std_logic makes the error go away signal prbs_fb  : std_logic;

begin
  
  process (clk)
  begin
    if reset = '1' then
      dout <= "00000000";
    elsif rising_edge(clk) then
      dout(7 downto 0) <= dout(6 downto 0) & prbs_fb;
    end if; 
  end process;
    -- below is line 31
    prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
          
end architecture;

signal prbs_fb我可以通过将 的类型更改为 来消除错误std_logic。

类型定义unsigned(0 downto 0)对我来说更有意义，因为赋值的 RHS 是无符号的。代码似乎在推断赋值的 LHS 上的单个无符号位和赋值的 RHS 上的单个无符号位。

为什么第 31 行被视为聚合？逻辑运算符的输出应该是一位？

Cadence 所传达的信息有所不同；但它也对某事感到不满。

    prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
                                                    |
xmvhdl_p: *E,EXPTYP (design.vhd,31|52): expecting an expression of type UNSIGNED 87[8.3] 93[8.4].
xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.

这也消除了错误，但不清楚为什么 VHDL 需要命名关联（第三版 Ashenden 书第 4.12 节数组聚合称之为“命名关联”）来分配单个元素数组？

prbs_fb <= ( 0 => dout(7) xnor dout(5) xnor dout(4) xnor dout(3) );

我在 Vivado 上遇到错误。我正在尝试运行实现来对我的 Basys 板进行编程，但遇到以下错误：

[DRC MDRV-1] 多个驱动程序网络：Net ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/nextS[1] 具有多个驱动程序：ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_3/O 和 ScrlFSM/RLC2B/DER1/ DFF_R1/DFF1/Q_i_2/O。

这是我的顶级 VHDL：

architecture Structural of xxxxxxxxxxx is

    component WordTo4DigitDisplayDriver is
    port (
            WORD    : in  STD_LOGIC_VECTOR(15 downto 0);
            PULSE   : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            SEGMENT : out STD_LOGIC_VECTOR(0 to 6);
   ANODE   : out STD_LOGIC_VECTOR(3 downto 0)
        );
    end component;

    component PulseGenerator_1ms is
        port (
            CLK    : in  STD_LOGIC;
            PULSE  : out STD_LOGIC
        );
    end component;
   
    signal pulse_1ms : STD_LOGIC;

    component ScrollFSM is
        port (
            L       : in  STD_LOGIC;
            R       : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            RESET   : in  STD_LOGIC;
            DISPLAY : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
begin

    Wt4DDD: WordTo4DigitDisplayDriver
    port map (
        WORD    => SWITCH(15 downto 0),
        PULSE   => pulse_1ms,
        CLK     => CLK,
        SEGMENT => SEGMENT,
        ANODE   => ANODE
    );

    PulseGen: PulseGenerator_1ms
    port map (
        CLK   => CLK,
        PULSE => pulse_1ms
    );
   
    ScrlFSM: ScrollFSM
    port map (
        L       => BTNL,
        R       => BTNR,
        CLK     => CLK,
        RESET   => BTND,
        DISPLAY (1 downto 0) => LED(15 downto 14)
    );

end architecture;

我的 ScrollFSM 代码：

architecture Structural of ScrollFSM is

    component Reg_LOAD_CLR_2bit is
        port (
            D    : in  STD_LOGIC_VECTOR(1 downto 0);
            CLK  : in  STD_LOGIC;
            LOAD : in  STD_LOGIC;
            CLR  : in  STD_LOGIC;
            Q    : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
    signal currentS : STD_LOGIC_VECTOR(1 downto 0);
    signal nextS    : STD_LOGIC_VECTOR(1 downto 0);
   
    alias NS1 : STD_LOGIC is nextS(1);
    alias NS0 : STD_LOGIC is nextS(0);
    alias S1  : STD_LOGIC is currentS(1);
    alias S0  : STD_LOGIC is currentS(0);



begin

    NS1 <= (not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R);
   
    NS1 <= (S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R);
   
    RLC2B: Reg_LOAD_CLR_2bit
    port map (
        D => nextS,
        CLK => CLK,
        LOAD => '1',
        CLR => RESET,
        Q => currentS
    );

    DISPLAY <= currentS;

我的 DFF1 代码：

architecture Behavioral of DFF is

begin

    process (CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;

end architecture;

我仔细阅读了可能的原因，似乎我将多个输出捆绑在一起。我在我的顶层找不到任何这样的情况，所以我不确定问题是什么。我尝试解决顶层和 VHDL 其余部分中任何可能的错误，但仍然遇到相同的错误。

在 VHDL 体系结构声明区域中，我有时会使用嵌入式配置，例如for and_gate_inst : and_gate use entity work.and_gate(rtl);但当实例位于生成内部时，我不知道如何编写此嵌入式配置。也许这不受支持。我的代码示例中的嵌入式配置语句产生错误并且不正确：

library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
    port (
        inp1_i, inp2_i : in std_logic;
        out_o  : out std_logic
    );
end entity;
architecture rtl of and_gate is
begin
    out_o <= inp1_i and inp2_i;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
entity embedded_conf is
end entity embedded_conf;
library work;
architecture struct of embedded_conf is
    signal inp1, inp2, out1  : std_logic;
    component and_gate is
        port (
            inp1_i : in  std_logic;
            inp2_i : in  std_logic;
            out_o  : out std_logic
        );
    end component;
    for dummy_g for and_gate_inst : and_gate use entity work.and_gate(rtl); -- Not correct!!!
begin
    dummy_g: if true generate
        and_gate_inst : and_gate
            port map (
                inp1_i => inp1,
                inp2_i => inp2,
                out_o  => out1
            );
    end generate dummy_g;
end architecture;

有谁知道这个嵌入式配置必须是什么样子？

我不确定这个运算符是如何工作的。

例如，如果我有：

signal vector_a : std_logic_vector(4 downto 0) :=(others => '0');

vector_a <= vector_a(3 downto 0) & '1';

结果会是"0 0 0 0 1"还是"1 0 0 0 0"？

如果使用3 to 0代替3 downto 0，结果会改变吗？