Questa 出现此错误（在 EDA Playground 上使用 -2008 进行编译）
-- Compiling architecture rtl of foo
** Error: design.vhd(31): Type error resolving infix expression "xnor" as type ieee.NUMERIC_STD.UNSIGNED.
** Note: design.vhd(31): (vcom-1499) Aggregate with a single element association must use named association.
对于此示例代码
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is
port(
clk : in std_logic;
reset: in std_logic;
din : in std_logic;
dout: out unsigned(7 downto 0)
);
end entity foo;
architecture rtl of foo is
signal prbs_fb : unsigned(0 downto 0);
-- changing to std_logic makes the error go away signal prbs_fb : std_logic;
begin
process (clk)
begin
if reset = '1' then
dout <= "00000000";
elsif rising_edge(clk) then
dout(7 downto 0) <= dout(6 downto 0) & prbs_fb;
end if;
end process;
-- below is line 31
prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
end architecture;
signal prbs_fb我可以通过将 的类型更改为 来消除错误std_logic。
类型定义unsigned(0 downto 0)对我来说更有意义，因为赋值的 RHS 是无符号的。代码似乎在推断赋值的 LHS 上的单个无符号位和赋值的 RHS 上的单个无符号位。
为什么第 31 行被视为聚合？逻辑运算符的输出应该是一位？
Cadence 所传达的信息有所不同；但它也对某事感到不满。
prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
|
xmvhdl_p: *E,EXPTYP (design.vhd,31|52): expecting an expression of type UNSIGNED 87[8.3] 93[8.4].
xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.
这也消除了错误，但不清楚为什么 VHDL 需要命名关联（第三版 Ashenden 书第 4.12 节数组聚合称之为“命名关联”）来分配单个元素数组？
prbs_fb <= ( 0 => dout(7) xnor dout(5) xnor dout(4) xnor dout(3) );