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Abdur-Rahman Igram's questions

Martin Hope
Abdur-Rahman Igram
Asked: 2024-04-24 23:59:35 +0800 CST
  • 6

我在 Vivado 上遇到错误。我正在尝试运行实现来对我的 Basys 板进行编程，但遇到以下错误：

[DRC MDRV-1] 多个驱动程序网络：Net ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/nextS[1] 具有多个驱动程序：ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_3/O 和 ScrlFSM/RLC2B/DER1/ DFF_R1/DFF1/Q_i_2/O。

这是我的顶级 VHDL：


architecture Structural of xxxxxxxxxxx is

    component WordTo4DigitDisplayDriver is
    port (
            WORD    : in  STD_LOGIC_VECTOR(15 downto 0);
            PULSE   : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            SEGMENT : out STD_LOGIC_VECTOR(0 to 6);
   ANODE   : out STD_LOGIC_VECTOR(3 downto 0)
        );
    end component;

    component PulseGenerator_1ms is
        port (
            CLK    : in  STD_LOGIC;
            PULSE  : out STD_LOGIC
        );
    end component;
   
    signal pulse_1ms : STD_LOGIC;

    component ScrollFSM is
        port (
            L       : in  STD_LOGIC;
            R       : in  STD_LOGIC;
            CLK     : in  STD_LOGIC;
            RESET   : in  STD_LOGIC;
            DISPLAY : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
begin

    Wt4DDD: WordTo4DigitDisplayDriver
    port map (
        WORD    => SWITCH(15 downto 0),
        PULSE   => pulse_1ms,
        CLK     => CLK,
        SEGMENT => SEGMENT,
        ANODE   => ANODE
    );

    PulseGen: PulseGenerator_1ms
    port map (
        CLK   => CLK,
        PULSE => pulse_1ms
    );
   
    ScrlFSM: ScrollFSM
    port map (
        L       => BTNL,
        R       => BTNR,
        CLK     => CLK,
        RESET   => BTND,
        DISPLAY (1 downto 0) => LED(15 downto 14)
    );

end architecture;

我的 ScrollFSM 代码：

architecture Structural of ScrollFSM is

    component Reg_LOAD_CLR_2bit is
        port (
            D    : in  STD_LOGIC_VECTOR(1 downto 0);
            CLK  : in  STD_LOGIC;
            LOAD : in  STD_LOGIC;
            CLR  : in  STD_LOGIC;
            Q    : out STD_LOGIC_VECTOR(1 downto 0)
        );
    end component;
   
    signal currentS : STD_LOGIC_VECTOR(1 downto 0);
    signal nextS    : STD_LOGIC_VECTOR(1 downto 0);
   
    alias NS1 : STD_LOGIC is nextS(1);
    alias NS0 : STD_LOGIC is nextS(0);
    alias S1  : STD_LOGIC is currentS(1);
    alias S0  : STD_LOGIC is currentS(0);



begin

    NS1 <= (not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R);
   
    NS1 <= (S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R);
   
    RLC2B: Reg_LOAD_CLR_2bit
    port map (
        D => nextS,
        CLK => CLK,
        LOAD => '1',
        CLR => RESET,
        Q => currentS
    );

    DISPLAY <= currentS;

我的 DFF1 代码：

architecture Behavioral of DFF is

begin

    process (CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;

end architecture;

我仔细阅读了可能的原因，似乎我将多个输出捆绑在一起。我在我的顶层找不到任何这样的情况，所以我不确定问题是什么。我尝试解决顶层和 VHDL 其余部分中任何可能的错误，但仍然遇到相同的错误。

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