我对 Verilog 相当陌生，我正在努力熟悉它。我正在 Verilog 中构建 ALU，当我尝试将操作中的值分配给 时ALU_result reg，我收到标题上列出的错误。
parameter N = 8;
input [N-1:0] inA, inB;
input [3:0] op;
reg ALU_result[N-1:0] ;
always @(*)
case(op)
4'b0000:
begin
ALU_result = inA & inB ;
end
4'b0001:
begin
ALU_result = inA | inB ;
end
4'b0010:
begin
ALU_result = inA + inB ;
end
endcase
我得到的错误更具体。我用 icarus verilog 编译了 Verilog 代码。
library.v:39: error: Cannot assign to array ALU_result. Did you forget a word index?
library.v:43: error: Cannot assign to array ALU_result. Did you forget a word index?
library.v:47: error: Cannot assign to array ALU_result. Did you forget a word index?