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问题[verilog](coding)

Martin Hope
Mister Moron
Asked: 2025-04-03 04:33:53 +0800 CST
  • 6

假设我们正在尝试为模块编写名为 SC_TB 的 Verilog/SystemVerilog 测试台代码sample_code。有没有更实用的方法可以查看测试台上正在做什么reg B，wire Cw而无需为它们创建端口？

module sample_code(
   input A,
   output Z
);

   reg B;
   wire Cw;

   *stuff happens in this code*
endmodule

///测试台代码

module SC_TB();
   reg A;
   wire Z;
   
   sample_code SCInst(
      .A(A),
      .Z(Z)
   );
   initial begin
      A=0
      #x a=value;
   end

   initial begin
      $monitor(A,Z)
   end

目前，要查看“reg B”和“wire Cw”在做什么，我会为它们创建端口，然后将这些端口包含在我的测试台代码中。对于内部声明的 wires（sample_code 中的 Cw），我会将它们注释掉，然后创建一个具有类似名称的输出 wire 端口。对于内部声明的 reg（sample_code 中的 reg B），我还将创建一个输出 wire 端口，然后将内部 reg 分配到该 wire 端口。我的代码和基于 sample_code 和 SC_TB 的测试台代码最终看起来像这样。

module sample_code(
   input A,
   output Z,
   output wire Cw,
   output wire Bw
);

   reg B;
   //wire Cw;

   assign Bw = B;

   *stuff happens in this code*
endmodule

///测试台代码

module SC_TB();
   reg A;
   wire Z;
   wire Cw;
   wire Bw;
   
   sample_code SCInst(
      .A(A),
      .Z(Z),
      .Cw(Cw),
      .Bw(Bw)
   );

   initial begin
      A=0
      #x a=value;
   end

   initial begin
      $monitor(A,Z,Cw,Bw) //it doesnt have to be "monitor", "$display" or just the timing diagram works.
   end
verilog
Martin Hope
Mayank Neupane
Asked: 2025-04-03 03:16:35 +0800 CST
  • 7

我正在为 DE10-Lite FPGA 开发一个 Verilog 项目，该项目通过 SPI 与 3 轴加速度计连接。我为每个轴设置了单独的 SPI 模块 (spi_ee_config)：、x_info和y_info。z_info每个模块都输出自己的芯片选择 ( oSPI_CSN) 和时钟 ( oSPI_CLK) 信号。但是，当我尝试编译时，出现以下错误：

错误

所有 3 个轴的模块头

据我所知，这意味着多个模块正在尝试使用同一条线路，从而导致冲突。但由于我从 3 个轴读取数据，我不确定如何正确共享 SPI 总线而不出现此错误。

我应该如何构造 Verilog 代码，以便每次只有一个模块驱动 CS 和 CLK 线路？我应该手动多路复用输出吗？或者是否有更好的模式来处理共享同一总线的多个 SPI 模块？

任何指导或代码片段都将不胜感激。

代码问题：

这里存在冲突，因为所有 3 个 spi_ee_config_# 都使用相同的 SPI 控制器：

spi_ee_config_X x_info (            
                            .oSPI_CSN(GSENSOR_CS_N),
                            .oSPI_CLK(GSENSOR_SCLK)
    );

spi_ee_config_y y_info (            
                        .oSPI_CSN(GSENSOR_CS_N),
                        .oSPI_CLK(GSENSOR_SCLK)
);

spi_ee_config_z z_info (            
                        .oSPI_CSN(GSENSOR_CS_N),
                        .oSPI_CLK(GSENSOR_SCLK)
);

回到 spi_controller：

module spi_controller (     
input                             iRSTN;
input                             iSPI_CLK;
input                             iSPI_CLK_OUT;
input         [SI_DataL:0]  iP2S_DATA; 
input                           iSPI_GO;
output                        oSPI_END;
output  reg [SO_DataL:0]    oS2P_DATA;
//  SPI Side              
inout                             SPI_SDIO;
output                        oSPI_CSN;    <<<<<<
output                          oSPI_CLK;  <<<<<<<


//  Structural coding
assign read_mode = iP2S_DATA[SI_DataL];
assign write_address = spi_count[3];
assign oSPI_END = ~|spi_count;
assign oSPI_CSN = ~iSPI_GO;
assign oSPI_CLK = spi_count_en ? iSPI_CLK_OUT : 1'b1;
assign SPI_SDIO = spi_count_en && (!read_mode || write_address) ? iP2S_DATA[spi_count] : 1'bz;

always @ (posedge iSPI_CLK or negedge iRSTN) 
    if (!iRSTN)
    begin
        spi_count_en <= 1'b0;
        spi_count <= 4'hf;
    end
    else 
    begin
        if (oSPI_END)
            spi_count_en <= 1'b0;
        else if (iSPI_GO)
            spi_count_en <= 1'b1;
            
        if (!spi_count_en)  
        spi_count <= 4'hf;      
        else
            spi_count   <= spi_count - 4'b1;

    if (read_mode && !write_address)
          oS2P_DATA <= {oS2P_DATA[SO_DataL-1:0], SPI_SDIO};
    end

endmodule
verilog
Martin Hope
Subramanya Krishna
Asked: 2025-02-27 00:38:50 +0800 CST
  • 5

如何在系统 Verilog 中使用移位运算符编写零件选择表达式？
给定一个内存字

logic [0:8] memword;

如何在移位运算符中编写部分选择表达式 memword[i:j]？如果不使用移位运算符，您能建议其他表达式吗？

i 和 j 可以是任意索引表达式。我们将此内存字分配给另一个具有 |ij| 宽度的内存字。

考虑从左到右和从右到左的索引。

用例：为部分选择编写替代语句以进行编译器相关的优化

该内存可以在程序的任何地方使用

always @(posedge clk) begin
   if (memword[i:j]) begin
      mem2 = memword[i:j];
   end
end

主要用途是消除部分选择。

verilog
Martin Hope
Meir
Asked: 2025-02-04 21:44:02 +0800 CST
  • 5

来自 LRM：

23.3.3.1 端口强制 声明为输入（输出）但用作输出（输入）或输入输出的端口可以强制转换为输入输出。如果不强制转换为输入输出，则应发出警告。

LRM 没有意义，如果强制，即模拟器正在“后台”更改 rtl，则应该发出警告，难道不应该相反吗？如果不强制输入输出，编译应该会失败（如 lint 和综合）？

测试用例：https://www.edaplayground.com/x/VdmF

相关：当输入输出端口有时可以在 Verilog 中互换使用时，输入输出端口的确切标准是什么？

verilog
Martin Hope
Sertan Hakkı İmamoğlu
Asked: 2025-01-09 00:19:04 +0800 CST
  • 6

我需要这个来做学校项目。教授想要一个 LED 序列，如果为零x（这意味着sw为 0），则该序列将为：

0000000000000001
0000000000000010
0000000000000100
0000000000001000
0000000000010000
0000000000100000
0000000001000000
0000000010000000
0000000100000000
0000001000000000
0000010000000000
0000100000000000
0001000000000000
0010000000000000
0100000000000000
1000000000000000

如果不是，它就会反过来。现在我被困在测试台文件中，因为它没有显示向量中led看起来像步骤的变化。这是我的主要代码：

`timescale 1ns / 1ps

module main(
    output [15:0] led,
    input clk,
    input btnC,
    input sw
);

reg [15:0] state;
reg ovr;
reg x;
wire sec;

zaman timer (sec, clk, btnC);

initial begin
    state = 16'b0000000000000001;
    ovr = 1'b0;
    x = 0;
end

always @ (posedge clk) begin
    x <= sw;
    
    if (btnC == 1) begin
        state = 16'b0000000000000001;
        ovr = 1'b0;
    end
    else if (sec == 1) begin
        if (x == 0) begin
            {ovr,state} <= state << 1;
            if (ovr == 1'b1) begin
                state <= 16'b0000000000000001;
                ovr <= 1'b0;
            end
        end
        else if (x == 1) begin
            {state, ovr} <= state >> 1;
            if (ovr == 1'b1) begin
                state <= 16'b1000000000000000;
                ovr <= 1'b0;
            end
        end
    end
    
end
assign led = state;

endmodule

其子模块：

module zaman(
output Y,
input clock,
input reset
);

reg elapsed;
reg [25:0] state;

always @(posedge clock)
if (reset == 1) state <= 0;
else if (state == 50000000) state <= 0;// corresponds to 1 sec
else state <= state + 1;

always @(state)
if (state == 50000000) elapsed = 1;
else elapsed = 0;
assign Y = elapsed;

endmodule

和测试台文件：

`timescale 1ns / 1ps

module maintb;

reg clk;
reg btnC;
reg sw;
wire [15:0] led;
    
main uut(.led(led), .btnC(btnC), .sw(sw), .clk(clk));

always #5 clk = ~clk;

initial begin
    clk = 0;
    btnC = 0;
    sw = 0;
    
    btnC = 1;
    #10;
    btnC = 0;
    
    #160000000;
end

endmodule

我得到的只是这个模拟结果：

模拟结果

verilog
Martin Hope
daniel danino
Asked: 2025-01-03 03:50:43 +0800 CST
  • 7

我遇到了一个问题，即我的模拟中的缓冲区无法按预期工作。我尝试了一些测试并得到了以下结果。我在 Verilog 中创建了以不同方式生成两个缓冲区的代码：

module buffer(
    input wire clk,
    input wire ena,
    output wire buffer,
    output wire buffer2
);
reg buffer_reg = 1'b0;
reg buffer_next = 1'b0;
reg buffer2_reg = 1'b0;

assign buffer = buffer_reg;
assign buffer2 = buffer2_reg;

always @(*) begin
    buffer_next = ena;
end

always @(posedge clk) begin
    buffer_reg <= buffer_next;
    buffer2_reg <= ena;
end
endmodule

然后我使用以下测试台在 Modelsim 中对其进行模拟：

`timescale 1ns / 1ns
module buffer_tb();

localparam CLK_CYCLE = 8;

reg clk;
reg ena;
wire buffer;
wire buffer2;

buffer dut(
    .clk(clk),
    .ena(ena),
    .buffer(buffer),
    .buffer2(buffer2)
);

// Clock generation
initial begin
    clk = 1'b0;
end

always #(CLK_CYCLE/2) clk = ~clk;

// Test sequence
initial begin
    // Initialize signals
    ena = 0;

    // change ena values based on the posedge clk
    @(posedge clk) ena = 1;
    @(posedge clk) ena = 0;
        
    repeat(5) @(posedge clk);
        
    @(posedge clk) ena = 1;
    @(posedge clk) ena = 0;
    
    
    repeat(2) #CLK_CYCLE;
    
    // change ena values based on the CLK_CYCLE
    #(CLK_CYCLE) ena = 1;
    #CLK_CYCLE ena = 0;
  
    repeat(5) #CLK_CYCLE;
  
    #CLK_CYCLE ena = 1;
    #CLK_CYCLE ena = 0;

    // Allow simulation to run for a while
    #50 $stop;   // Stop simulation
end
endmodule

我在模拟中得到了以下结果：

在 modelsim 中模拟缓冲区

有人能解释一下为什么buffer2当我使用posedge clk和使用时会得到不同的结果吗CLK_CYCLE？

verilog
Martin Hope
Florinlego
Asked: 2024-12-26 17:56:34 +0800 CST
  • 6

我已经实现了一个 BCD 转换器，可以在两台不同的 PC 上工作：

  • 一台电脑（AMD Ryzen 7 3700X 8 核处理器、GeForce RTX 2070 SUPER、32GB 内存 - Windows 10）
  • 一台笔记本电脑（英特尔 i7-1165G7 处理器，32GB 内存 - Windows 11 PRO）

作为 IDE，我在两台计算机上都使用了 Vivado 2024.2，并使用了 Basys3 开发板进行实现。

在 BCD 上运行行为模拟（两台 PC 的代码相同）后，无论我在计算机上做什么，输出都保持在 X，但在笔记本电脑上，输出会根据实施的设计正确更改。对于两台 PC，从综合开始，结果都是相同的，并且在生成比特流并将程序加载到板上后，程序可以正常工作。

为了完整起见，我还将包括设计的代码：

module counter #(parameter SIZE = 4) (
        input clk,
        input rst,
        input en,
        output reg [SIZE-1:0] out
    );
    
    always @(posedge clk, negedge rst) begin
    
        if(!rst)
            out <= 0;
        else
            if (en) out <= out + 1;
    
    end
    
endmodule

module loadRegister #(DATA_SIZE = 1, REG_SIZE = 2) (
        input clk,
        input rst,
        input [DATA_SIZE-1:0] Din,
        input Sin,
        input [REG_SIZE - 1 : 0] cellAdr,
        input serialLoad,
        input parallelLoad,
        output reg [DATA_SIZE * (2 ** REG_SIZE) - 1 : 0] data
    );
    
    always @(posedge clk) begin
    
        if(!rst) data <= 0;
        
        else if(parallelLoad) begin
        
            data[DATA_SIZE*cellAdr+:DATA_SIZE] <= Din;
        
        end
        
        else if(serialLoad) begin
        
            data <= {data[DATA_SIZE * (2 ** REG_SIZE) - 2 : 0],Sin};
        
        end
        
        else begin
        
            data <= data;
        
        end
    
    end
    
endmodule

module Binary2BCDTranscoder #(parameter INPUT_SIZE = 12, parameter OUTPUT_DIGITS = 4, parameter ICNTR_SIZE = 4, parameter JCNTR_SIZE = 2) (
        input clk,
        input rst,
        input convStart,
        input [INPUT_SIZE-1:0] data,
        output reg convDone,
        output reg [4 * OUTPUT_DIGITS - 1:0] convOut 
    );
    
    localparam WAIT = 2'b00;
    localparam CONV_CHK = 2'b01;
    localparam FINISHED = 2'b11;
    
    reg iRst, jRst, iEn, jEn;
    wire [ICNTR_SIZE-1:0] i;
    wire [JCNTR_SIZE-1:0] j;
    
    reg [1:0] state, next_state;
    reg [INPUT_SIZE-1:0] inner_in;
    
    reg loadRegRst;
    reg [3:0] loadRegDin;
    reg loadRegSin;
    reg loadRegSerial, loadRegParallel;
    reg [1:0] loadRegCellAdr;
    
    wire [4 * OUTPUT_DIGITS - 1:0] inner_out;
    
    always @(posedge clk) begin
    
        if(!rst) state <= WAIT;
        
        else state <= next_state;
    
    end
    
    always @(posedge clk) begin
    
        if(!rst) inner_in <= 0;
    
        else if(state==WAIT) inner_in <= data;
        
    end
    
    always @(posedge clk) begin
    
        if(state==CONV_CHK & convDone) convOut <= inner_out;
    
    end
    
    counter #(.SIZE(ICNTR_SIZE)) iCounter (
        .clk(clk),
        .rst(iRst),
        .en(iEn),
        .out(i)
    );
    
    counter #(.SIZE(JCNTR_SIZE)) jCounter (
        .clk(clk),
        .rst(jRst),
        .en(jEn),
        .out(j)
    );
    
    loadRegister #(.DATA_SIZE(4),.REG_SIZE(2)) innerOutReg (
        .clk(clk),
        .rst(loadRegRst),
        .Din(loadRegDin),
        .Sin(loadRegSin),
        .serialLoad(loadRegSerial),
        .parallelLoad(loadRegParallel),
        .cellAdr(loadRegCellAdr),
        .data(inner_out)
    );
        
    always @(*) begin
    
        case(state)
        
            WAIT: begin
            
                convDone = 0;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
                next_state = convStart ? CONV_CHK : WAIT;
            
            end
            
            CONV_CHK: begin
                
                if(i == INPUT_SIZE) begin
                    convDone = 1;
                    next_state = FINISHED;
                    iRst = 0;
                    jRst = 0;
                    iEn = 0;
                    jEn = 0;
                end
                
                else if(j == OUTPUT_DIGITS-1) begin
                    next_state = CONV_CHK;
                    convDone = 0;
                    iRst = 1;
                    jRst = 0;
                    iEn = 1;
                    jEn = 0;
                end
                
                else begin
                    next_state = CONV_CHK;
                    convDone = 0;
                    iRst = 1;
                    jRst = 1;
                    iEn = 0;
                    jEn = 1;
                end
            
            end
            
            FINISHED: begin
            
                next_state = WAIT;
                convDone = 1;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
                
            end
            
            default: begin
                next_state = WAIT;
                convDone = 0;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
            end
        
        endcase
    
    end
    
    always @(*) begin
    
        case(state)
        
            WAIT: begin
                loadRegRst = 0;
                loadRegDin = 0;
                loadRegSin = 0;
                loadRegParallel = 0;
                loadRegSerial = 0;
                loadRegCellAdr = 0;
            end
            
            CONV_CHK: begin
            
                loadRegRst = 1;
            
                if (iEn) begin
                    loadRegDin = 0;
                    loadRegSin = inner_in[INPUT_SIZE-1-i];
                    loadRegParallel = 0;
                    loadRegSerial = 1;
                    loadRegCellAdr = 0;
                end
                
                else if (jEn) begin
                    
                    if(inner_out[4*j+:4] >= 5) begin
                    
                        loadRegDin = inner_out[4*j+:4] + 3;
                        loadRegSin = 0;
                        loadRegParallel = 1;
                        loadRegSerial = 0;
                        loadRegCellAdr = j; 
                    
                    end
                    
                    else begin
                    
                        loadRegDin = 0;
                        loadRegSin = 0;
                        loadRegParallel = 0;
                        loadRegSerial = 0;
                        loadRegCellAdr = 0;
                    
                    end
                    
                end
                
                else begin
                    loadRegDin = 0;
                    loadRegSin = 0;
                    loadRegParallel = 0;
                    loadRegSerial = 0;
                    loadRegCellAdr = 0;
                end
            
            end
            
            FINISHED: begin
            
                loadRegRst = 1;
                loadRegDin = 0;
                loadRegSin = 0;
                loadRegParallel = 0;
                loadRegSerial = 0;
                loadRegCellAdr = 0;
            
            end
            
            default: begin
            
                loadRegRst = 0;
                loadRegDin = 0;
                loadRegSin = 0;
                loadRegParallel = 0;
                loadRegSerial = 0;
                loadRegCellAdr = 0;
            
            end
        
        endcase
    
    end
    
endmodule

module Bin2BCDTest();

reg clk, rst, convStart;
reg [11:0] data;

wire convDone;
wire [15:0] convOut;
    
Binary2BCDTranscoder #(.INPUT_SIZE(12),.OUTPUT_DIGITS(4),.ICNTR_SIZE(4),.JCNTR_SIZE(2)) dut (
    .clk(clk),
    .rst(rst),
    .convStart(convStart),
    .data(data),
    .convDone(convDone),
    .convOut(convOut)
);

initial begin
    clk = 0;
    forever #5 clk = !clk;
end

initial begin 
    rst = 0;
    convStart = 0;
    
    #10 rst = 1;
    
    #10 data = 1023;
    #10 convStart = 1;
    #20 convStart = 0;
    
    #1000;
    
    #10 data = 512;
    #10 convStart = 1;
    #20 convStart = 0;
    
    #1000;
    
    #10 data = 3683;
    #10 convStart = 1;
    #20 convStart = 0;
    
    #1000;
    
    #10 data = 4091;
    #10 convStart = 1;
    #20 convStart = 0;
    
    #1000;
    
    #10 data = 4090;
    #10 convStart = 1;
    #20 convStart = 0;
    
    #1000;
    $stop;
end

endmodule

为什么会发生这种情况？这是两个不同操作系统之间的问题吗？如果是这样，为什么它只影响模拟而不影响综合？

verilog
Martin Hope
Florinlego
Asked: 2024-12-20 20:55:06 +0800 CST
  • 6

我定义了一个二进制到 BCD 转换器，用于 Basys 3 开发板。在模拟中，结果符合预期，并且完全遵循时序。

我将 BCD 转换器包含在顶部模块中，在那里我使用通过另一个模块创建的输入脉冲启动转换过程。

在船上，结果很奇怪，因为大多数输入值都给出完整的零，唯一的例外是 1，它显示 BCD 值为 15|15|15|14。

因为问题仅存在于板上，所以我相信模块的合成存在问题，但我还无法找出原因。

Synthesis 向我发出以下警告：

[Synth 8-567] referenced signal 'i' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":80]

[Synth 8-567] referenced signal 'j' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":80]

[Synth 8-567] referenced signal 'state' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":150]

[Synth 8-567] referenced signal 'iEn' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":150]

[Synth 8-567] referenced signal 'inner_in' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":150]

[Synth 8-567] referenced signal 'jEn' should be on the sensitivity list ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":150]

[Synth 8-327] inferring latch for variable 'inner_out_reg' ["C:/Xilinx/VivadoProjects/BCD/BCD.srcs/sources_1/new/Binary2BCDTranscoder.v":155]

[Synth 8-7080] Parallel synthesis criteria is not met

以下是BCD转换器代码：

`timescale 1ns / 1ps

module Binary2BCDTranscoder #(parameter INPUT_SIZE = 12, parameter OUTPUT_DIGITS = 4, parameter ICNTR_SIZE = 4, parameter JCNTR_SIZE = 2) (
        input clk,
        input rst,
        input convStart,
        input [INPUT_SIZE-1:0] data,
        output reg convDone,
        output reg [4 * OUTPUT_DIGITS - 1:0] convOut 
    );
    
    localparam WAIT = 2'b00;
    localparam CONV_CHK = 2'b01;
    localparam FINISHED = 2'b11;
    
    reg iRst, jRst, iEn, jEn;
    wire [ICNTR_SIZE-1:0] i;
    wire [JCNTR_SIZE-1:0] j;
    
    reg [1:0] state, next_state;
    reg [INPUT_SIZE-1:0] inner_in;
    reg [4 * OUTPUT_DIGITS - 1:0] inner_out;
    
    always @(posedge clk) begin
    
        if(!rst) state <= WAIT;
        
        else state <= next_state;
    
    end
    
    always @(posedge clk) begin
    
        if(!rst) inner_in <= 0;
    
        else if(convDone) inner_in <= data;
        
    end
    
    always @(posedge convDone) begin
    
        convOut <= inner_out;
    
    end
    
    counter #(.SIZE(ICNTR_SIZE)) iCounter (
        .clk(clk),
        .rst(iRst),
        .en(iEn),
        .out(i)
    );
    
    counter #(.SIZE(JCNTR_SIZE)) jCounter (
        .clk(clk),
        .rst(jRst),
        .en(jEn),
        .out(j)
    );
        
    always @(state, convStart) begin
    
        case(state)
        
            WAIT: begin
            
                convDone = 1;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
                next_state = convStart ? CONV_CHK : WAIT;
            
            end
            
            CONV_CHK: begin
                
                if(i == INPUT_SIZE) begin
                    convDone = 1;
                    next_state = FINISHED;
                    iRst = 0;
                    jRst = 0;
                    iEn = 0;
                    jEn = 0;
                end
                
                else if(j == OUTPUT_DIGITS-1) begin
                    next_state = CONV_CHK;
                    convDone = 0;
                    iRst = 1;
                    jRst = 0;
                    iEn = 1;
                    jEn = 0;
                end
                
                else begin
                    next_state = CONV_CHK;
                    convDone = 0;
                    iRst = 1;
                    jRst = 1;
                    iEn = 0;
                    jEn = 1;
                end
            
            end
            
            FINISHED: begin
            
                next_state = WAIT;
                convDone = 1;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
                
            end
            
            default: begin
                next_state = WAIT;
                convDone = 1;
                iRst = 0;
                iEn = 0;
                jRst = 0;
                jEn = 0;
            end
        
        endcase
    
    end
    
    always @(i,j) begin
    
        case(state)
        
            WAIT: begin
                inner_out = 0;
            end
        
            CONV_CHK: begin
                if(iEn) begin
                    inner_out = {inner_out[4*OUTPUT_DIGITS - 2 : 0], inner_in[INPUT_SIZE - 1 - i]};
                end
                
                else if(jEn) begin
                    inner_out = inner_out;
                    if(inner_out[4*j+:4] >= 5) inner_out[4*j+:4] = inner_out[4*j+:4] + 3;
                end
                
                else begin
                    inner_out = inner_out;
                end
            end
            
            FINISHED: begin
                inner_out = 0;
            end
        
            default: begin
                inner_out = 0;
            end 
        
        
        endcase
    
    end
endmodule

顶层模块如下：

module top(
        input clk,
        input rst,
        input convStart,
        input [11:0] data,
        output convDone,
        output [15:0] convOut 
    );

    wire convPulse;
    wire [9:0] clkDivOut;
    
    counter #(.SIZE(10)) CLK_DIVIDER(
        .clk(clk),
        .rst(!rst),
        .en(1'b1),
        .out(clkDivOut)
    );
    
    pulseCreator #(.NUM_BITS(2)) convStartPulse (
        .clk(clkDivOut[9]),
        .in(convStart),
        .out(convPulse),
        .regOutput()
    );
    
    Binary2BCDTranscoder #(.INPUT_SIZE(12),.OUTPUT_DIGITS(4),.ICNTR_SIZE(4),.JCNTR_SIZE(2)) B2BCD (
        .clk(clkDivOut[9]),
        .rst(!rst),
        .convStart(convPulse),
        .data(data),
        .convDone(convDone),
        .convOut(convOut)
    );
    
endmodule

为了完整起见，这里是计数器和脉冲发生器的代码：

module counter #(parameter SIZE = 4) (
        input clk,
        input rst,
        input en,
        output reg [SIZE-1:0] out
    );
    
    always @(posedge clk) begin
    
        if(!rst)
            out <= 0;
        else
            if (en) out <= out + 1;
    
    end
    
endmodule

module serialRegister #(SIZE = 4)(
        input clk,
        input rst,
        input in,
        input en,
        output reg [SIZE-1:0] out
    );
    
    always @(posedge clk, negedge rst) begin
    
        if(!rst) begin
        
            out <= 0;
        
        end
        
        else begin
        
            if(en) out <= {out[SIZE-2:0],in};
            
        end

    end
    
endmodule

module pulseCreator #(NUM_BITS=3) (
        input clk,
        input in,
        output out,
        output [NUM_BITS-1:0] regOutput
    );
    
    //wire [NUM_BITS-1:0] regOutput;
    
    serialRegister #(.SIZE(NUM_BITS)) pulseReg(
        .clk(clk),
        .rst(in),
        .en(in),
        .in(in),
        .out(regOutput)
    );
    
    assign out = in & !regOutput[NUM_BITS-1];

endmodule
verilog
Martin Hope
Arjun Ram
Asked: 2024-12-17 21:29:45 +0800 CST
  • 6

这是我的设计和测试台环境代码。

这是设计模块：

module router_1x3 (
    input wire clk,
    input wire rst,
    input wire [7:0] data_in,  // 8-bit data input
    input wire [1:0] sel,      // 2-bit select signal
    output reg [7:0] out0,     // Output channel 0
    output reg [7:0] out1,     // Output channel 1
    output reg [7:0] out2      // Output channel 2
);

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            out0 <= 8'b0; // Reset output 0
            out1 <= 8'b0; // Reset output 1
            out2 <= 8'b0; // Reset output 2
        end else begin
            case (sel)
                2'b00: begin
                    out0 <= data_in;
                    out1 <= 8'b0;
                    out2 <= 8'b0;
                end
                2'b01: begin
                    out0 <= 8'b0;
                    out1 <= data_in;
                    out2 <= 8'b0;
                end
                2'b10: begin
                    out0 <= 8'b0;
                    out1 <= 8'b0;
                    out2 <= data_in;
                end
                default: begin
                    out0 <= 8'b0;
                    out1 <= 8'b0;
                    out2 <= 8'b0;
                end
            endcase
        end
    end

endmodule

接口.sv

interface intf();
    logic clk;
    logic rst;
    logic [7:0] data_in;
    logic [1:0] sel;
    logic [7:0] out0;
    logic [7:0] out1;
    logic [7:0] out2;
endinterface

交易.sv

class transaction;
  rand bit [7:0] data_in;
  rand bit [1:0] sel;
  bit [7:0] out0;
  bit [7:0] out1;
  bit [7:0] out2;
  
  constraint valid_sel {sel <= 2'b10;}
  
  function void display(string name);
    $display("---------- %s --------- %t", name, $time);
    $display("data_in=%h, sel=%h, out0=%h, out1=%h, out2=%h", 
             data_in, sel, out0, out1, out2);
  endfunction
endclass

发电机.sv

class generator;
  
    transaction tx;
    mailbox gen2drv;
  
    // Constructor
    function new(mailbox gen2drv);
        this.gen2drv = gen2drv;
    endfunction

    task main();
        tx = new();
      if (tx.randomize()) begin
        tx.display("generator");
        gen2drv.put(tx);
        
        end
    endtask
endclass

驱动程序

class driver;
  transaction trans;
  virtual intf vif;
  
  mailbox gen2driv;
  
  function new(virtual intf vif, mailbox gen2driv);
    this.vif = vif;
    this.gen2driv = gen2driv;
  endfunction
  
  task main();
    
    repeat(1)
      begin
        
        gen2driv.get(trans);
        
        trans.display("Driver");
        
//         vif.data_in = trans.data_in;
//         vif.sel = trans.sel;
        
//         vif.out0 = trans.out0;
//      vif.out1 = trans.out1;
//         vif.out2 = trans.out2 ;
        
        vif.data_in <= trans.data_in;
        vif.sel <= trans.sel;
        
        vif.out0 <= trans.out0;
        vif.out1 <= trans.out1;
        vif.out2 <= trans.out2 ;
        
        
        
      end
  endtask
  
endclass

监视器

class monitor;
  virtual intf vif;
  mailbox mon2sbc;
  transaction trans;
  function new(virtual intf vif, mailbox mon2sbc);
    this.vif = vif;
    this.mon2sbc = mon2sbc;
    
  endfunction
  
  task main();
    repeat(1)
      #3;
      begin
        
        trans = new();
        trans.data_in = vif.data_in;
        trans.sel = vif.sel;
        
//         trans.out0 = vif.out0;
//         trans.out1 = vif.out1;
//         trans.out2 = vif.out2;
        
         vif.out0 = trans.out0;
         vif.out1 = trans.out1;
         vif.out2 = trans.out2;
        
        
        mon2sbc.put(trans);
        #1
        trans.display("Monitor");
      end
  endtask
endclass

记分牌.sv

class scoreboard;
   mailbox mon2sbc;
   transaction trans;
  function new(mailbox mon2sbc);
    this.mon2sbc = mon2sbc;
    
  endfunction
  
  task main();
    
    repeat(1)
      begin
        
        mon2sbc.get(trans);
        

        trans.display("Scoreboard");
        
          
      end
  endtask
   
endclass

环境.sv

`include "transaction.sv"
`include "generator.sv"
`include "driver.sv"
`include "scoreboard.sv"
`include "monitor.sv"

class environment;// it's complete environment of dut
                    // which is contain all component of testbench and connect tham  
  generator gen;    
  driver driv;
  monitor mon;
  scoreboard scb;
  
  mailbox m1;
  mailbox m2;
  
  virtual intf vif;
  
  function new(virtual intf vif);
    this.vif = vif;
    
    m1 = new();
    m2 = new();
    gen = new(m1);
    driv = new(vif,m1);
    mon = new(vif, m2);
    scb = new(m2);
    
  endfunction
  
  task test();
    fork
      gen.main();
      driv.main();
      mon.main();
      scb.main();
      
    join_none
  endtask
  
  task run;
    test();
    #100
    $finish;
  endtask
  
endclass

测试文件

`include "environment.sv"

program test(intf i_intf);//this connect interface to testbech environment
  environment env;
  
  initial
  begin
    env = new(i_intf);
    env.run();
    
  end
endprogram

测试台.sv

// Code your testbench here
// or browse Examples
`include "interface.sv"
`include "test.sv"

module tbench_top;
  intf router_vif();
  test t1(router_vif);
  
 router_1x3 dut (
        .clk(router_vif.clk),
        .rst(router_vif.rst),
        .data_in(router_vif.data_in),
        .sel(router_vif.sel),
        .out0(router_vif.out0),
        .out1(router_vif.out1),
        .out2(router_vif.out2)
    );

  
  // Clock generation
    initial begin
        router_vif.clk = 0;
        forever #5 router_vif.clk = ~router_vif.clk;
    end

    // Reset logic
    initial begin
        router_vif.rst = 1;
        #20;
        router_vif.rst = 0;
    end

  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars;
    end
  
endmodule

通过在 eda 中运行此代码（代码链接： https: //edaplayground.com/x/F7jS）我得到以下输出

ERNEL: ASDB file was created in location /home/runner/dataset.asdb
# KERNEL: ---------- generator ---------                    0
# KERNEL: data_in=35, sel=2, out0=00, out1=00, out2=00
# KERNEL: ---------- Driver ---------                    0
# KERNEL: data_in=35, sel=2, out0=00, out1=00, out2=00
# KERNEL: ---------- Scoreboard ---------                    3
# KERNEL: data_in=35, sel=2, out0=00, out1=00, out2=00
# KERNEL: ---------- Monitor ---------                    4
# KERNEL: data_in=35, sel=2, out0=00, out1=00, out2=00
# RUNTIME: Info: RUNTIME_0068 environment.sv (44): $finish called.

正如我所料，当监视器运行时，out2 = 35，但没有给出。

请建议我需要在代码中更改哪些内容？

verilog