如果可以将 linuxHyper-V
来宾 VM 转换为*.iso
文件,那么我可以从该映像文件创建可启动的 USB。通过谷歌我发现了以下工具:
有人可以分享他在这个话题上的经验吗?如何转换hvdx
->iso
或hvdx
-> hvd
-> iso
?
Windows 沙盒对我来说非常有用;拥有一个我用来尝试的即时容器很棒,这是一个了不起的功能,但我无法理解为什么商店应用程序在这里不起作用。我想知道这里是否有人有原因:
Windows Sandbox 从来没有太多的文档。看起来,一些稀疏的文档被放在了微软的网站上,然后我就再也没有听到过更多的信息。很高兴知道上述(或相关信息)的答案,谢谢。
Hyper-V 是否具有与标题 Oracle VirtualBox HOST KEY (default: ) 类似的功能,例如,当在来宾操作系统上处于全屏模式时right Ctrl
启用切换打开的主机窗口?left Ctrl + Tab
我正在尝试在 Windows 11 Hyper-V VM 中安装 Arch Linux。我使用的 ISO 是 archlinux-2022.06.01-x86_64.iso。
启动虚拟机时,它会显示一个菜单,我可以在其中进行选择
我选择第一个。然后安装挂在黑屏上。我没有得到命令提示符。在 Hyper-V 管理器中,我可以看到 VM 正在使用一些 CPU(它说 8%)。我让它运行了 15 分钟,但没有任何反应。
我已经在 VM 上禁用了安全启动,因为我知道您需要这样做。
我有一个运行良好的 Ubuntu VM,fwiw。
为什么会挂?
编辑:这些是 Hyper-V 设置。这是第 2 代虚拟机。
我正在尝试在 Windows 10 中运行 WSL。但是,这样做会返回一个模糊的The specified module could not be found
错误。我最初认为这是 Docker 的问题,直到我尝试独立运行 WSL。
我卸载了我的 WSL 实例(以及 Docker)的所有痕迹,然后尝试从 Windows 商店重新安装它们。运行该ubuntu
命令会产生以下输出:
PS C:\Users\Jesse> ubuntu
Installing, this may take a few minutes...
WslRegisterDistribution failed with error: 0x8007007e
Error: 0x8007007e The specified module could not be found.
Press any key to continue...
wsl --status
显示以下输出:
PS C:\Users\Jesse> wsl --status
Default Version: 2
Windows Subsystem for Linux was last updated on 3/29/2022
WSL automatic updates are on.
Kernel version: 5.10.102.1
这是我的 Windows 版本:
Edition Windows 10 Pro
Version 21H2
Installed on 12/24/2021
OS build 19044.1645
Experience Windows Feature Experience Pack 120.2212.4170.0
这是 的输出bcdedit /v
。我不知道它是否真的相关,但另一个关于 WSL 困难的超级用户问题包括它。
PS C:\Users\Jesse> bcdedit /v
Windows Boot Manager
--------------------
identifier {9dea862c-5cdd-4e70-acc1-f32b344d4795}
device partition=\Device\HarddiskVolume2
path \EFI\MICROSOFT\BOOT\BOOTMGFW.EFI
description Windows Boot Manager
locale en-US
inherit {7ea2e1ac-2e61-4728-aaa3-896d9d0a9f0e}
default {65875d57-62bf-11ec-bef5-a8a1599b691e}
resumeobject {65875d56-62bf-11ec-bef5-a8a1599b691e}
displayorder {65875d57-62bf-11ec-bef5-a8a1599b691e}
{65875d5a-62bf-11ec-bef5-a8a1599b691e}
toolsdisplayorder {b2721d73-1db4-4c62-bf78-c548a880142d}
timeout 1
displaybootmenu No
customactions 0x1000044000001
0x54000001
custom:54000001 {65875d5a-62bf-11ec-bef5-a8a1599b691e}
Windows Boot Loader
-------------------
identifier {65875d57-62bf-11ec-bef5-a8a1599b691e}
device partition=C:
path \windows\system32\winload.efi
description Windows 10
locale en-US
inherit {6efb52bf-1766-41db-a6b3-0ee5eff72bd7}
recoverysequence {65875d58-62bf-11ec-bef5-a8a1599b691e}
displaymessageoverride Recovery
recoveryenabled Yes
isolatedcontext Yes
allowedinmemorysettings 0x15000075
osdevice partition=C:
systemroot \windows
resumeobject {65875d56-62bf-11ec-bef5-a8a1599b691e}
nx OptIn
bootmenupolicy Legacy
hypervisorlaunchtype Auto
Windows Boot Loader
-------------------
identifier {65875d5a-62bf-11ec-bef5-a8a1599b691e}
device ramdisk=[R:]\sources\recoveryboot.wim,{65875d5b-62bf-11ec-bef5-a8a1599b691e}
path \WINDOWS\SYSTEM32\BOOT\WINLOAD.efi
description LT_Recovery
locale EN_US
osdevice ramdisk=[R:]\sources\recoveryboot.wim,{65875d5b-62bf-11ec-bef5-a8a1599b691e}
systemroot \WINDOWS
detecthal Yes
winpe Yes
这是输出coreinfo64
:
Coreinfo v3.52 - Dump information on system CPU and memory topology
Copyright (C) 2008-2021 Mark Russinovich
Sysinternals - www.sysinternals.com
AMD Ryzen Threadripper 2950X 16-Core Processor
AMD64 Family 23 Model 8 Stepping 2, AuthenticAMD
Microcode signature: 00000000
HTT * Multicore
CET - Supports Control Flow Enforcement Technology
Kernel CET - Kernel-mode CET Enabled
User CET - User-mode CET Allowed
HYPERVISOR * Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
SGX - Supports Intel SGX
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP * Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS - Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT * Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a * Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX instruction extensions
AVX2 * Supports AVX2 instruction extensions
AVX-512-F - Supports AVX-512 Foundation instructions
AVX-512-DQ - Supports AVX-512 double and quadword instructions
AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF - Supports AVX-512 prefetch instructions
AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD - Supports AVX-512 conflict detection instructions
AVX-512-BW - Supports AVX-512 byte and word instructions
AVX-512-VL - Supports AVX-512 vector length instructions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED * Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX * Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR - Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI - Implements MSR for power management
TM - Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE - Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended).
Maximum implemented address width: 48 bits (virtual), 48 bits (physical).
Processor signature: 00800F82
Logical to Physical Processor Map:
**------------------------------ Physical Processor 0 (Hyperthreaded)
--**---------------------------- Physical Processor 1 (Hyperthreaded)
----**-------------------------- Physical Processor 2 (Hyperthreaded)
------**------------------------ Physical Processor 3 (Hyperthreaded)
--------**---------------------- Physical Processor 4 (Hyperthreaded)
----------**-------------------- Physical Processor 5 (Hyperthreaded)
------------**------------------ Physical Processor 6 (Hyperthreaded)
--------------**---------------- Physical Processor 7 (Hyperthreaded)
----------------**-------------- Physical Processor 8 (Hyperthreaded)
------------------**------------ Physical Processor 9 (Hyperthreaded)
--------------------**---------- Physical Processor 10 (Hyperthreaded)
----------------------**-------- Physical Processor 11 (Hyperthreaded)
------------------------**------ Physical Processor 12 (Hyperthreaded)
--------------------------**---- Physical Processor 13 (Hyperthreaded)
----------------------------**-- Physical Processor 14 (Hyperthreaded)
------------------------------** Physical Processor 15 (Hyperthreaded)
Logical Processor to Socket Map:
******************************** Socket 0
Logical Processor to NUMA Node Map:
******************************** NUMA Node 0
- NUMA Node 1
Approximate Cross-NUMA Node Access Cost (relative to fastest):
00 01
00: 1.3 1.0
01: 0.0 0.0
Logical Processor to Cache Map:
**------------------------------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------ Instruction Cache 0, Level 1, 64 KB, Assoc 4, LineSize 64
**------------------------------ Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64
********------------------------ Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
--**---------------------------- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---------------------------- Instruction Cache 1, Level 1, 64 KB, Assoc 4, LineSize 64
--**---------------------------- Unified Cache 2, Level 2, 512 KB, Assoc 8, LineSize 64
----**-------------------------- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-------------------------- Instruction Cache 2, Level 1, 64 KB, Assoc 4, LineSize 64
----**-------------------------- Unified Cache 3, Level 2, 512 KB, Assoc 8, LineSize 64
------**------------------------ Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------ Instruction Cache 3, Level 1, 64 KB, Assoc 4, LineSize 64
------**------------------------ Unified Cache 4, Level 2, 512 KB, Assoc 8, LineSize 64
--------**---------------------- Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**---------------------- Instruction Cache 4, Level 1, 64 KB, Assoc 4, LineSize 64
--------**---------------------- Unified Cache 5, Level 2, 512 KB, Assoc 8, LineSize 64
--------********---------------- Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
----------**-------------------- Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**-------------------- Instruction Cache 5, Level 1, 64 KB, Assoc 4, LineSize 64
----------**-------------------- Unified Cache 7, Level 2, 512 KB, Assoc 8, LineSize 64
------------**------------------ Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------ Instruction Cache 6, Level 1, 64 KB, Assoc 4, LineSize 64
------------**------------------ Unified Cache 8, Level 2, 512 KB, Assoc 8, LineSize 64
--------------**---------------- Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**---------------- Instruction Cache 7, Level 1, 64 KB, Assoc 4, LineSize 64
--------------**---------------- Unified Cache 9, Level 2, 512 KB, Assoc 8, LineSize 64
----------------**-------------- Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**-------------- Instruction Cache 8, Level 1, 64 KB, Assoc 4, LineSize 64
----------------**-------------- Unified Cache 10, Level 2, 512 KB, Assoc 8, LineSize 64
----------------********-------- Unified Cache 11, Level 3, 8 MB, Assoc 16, LineSize 64
------------------**------------ Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------ Instruction Cache 9, Level 1, 64 KB, Assoc 4, LineSize 64
------------------**------------ Unified Cache 12, Level 2, 512 KB, Assoc 8, LineSize 64
--------------------**---------- Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**---------- Instruction Cache 10, Level 1, 64 KB, Assoc 4, LineSize 64
--------------------**---------- Unified Cache 13, Level 2, 512 KB, Assoc 8, LineSize 64
----------------------**-------- Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**-------- Instruction Cache 11, Level 1, 64 KB, Assoc 4, LineSize 64
----------------------**-------- Unified Cache 14, Level 2, 512 KB, Assoc 8, LineSize 64
------------------------**------ Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------ Instruction Cache 12, Level 1, 64 KB, Assoc 4, LineSize 64
------------------------**------ Unified Cache 15, Level 2, 512 KB, Assoc 8, LineSize 64
------------------------******** Unified Cache 16, Level 3, 8 MB, Assoc 16, LineSize 64
--------------------------**---- Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**---- Instruction Cache 13, Level 1, 64 KB, Assoc 4, LineSize 64
--------------------------**---- Unified Cache 17, Level 2, 512 KB, Assoc 8, LineSize 64
----------------------------**-- Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**-- Instruction Cache 14, Level 1, 64 KB, Assoc 4, LineSize 64
----------------------------**-- Unified Cache 18, Level 2, 512 KB, Assoc 8, LineSize 64
------------------------------** Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------** Instruction Cache 15, Level 1, 64 KB, Assoc 4, LineSize 64
------------------------------** Unified Cache 19, Level 2, 512 KB, Assoc 8, LineSize 64
Logical Processor to Group Map:
******************************** Group 0
以下是一些其他相关事实:
vmsmb.dll
可能是问题的一部分。wsl -l -v
表明Windows Subsystem for Linux has no installed distributions.
有小费吗?
我知道:
我相信有些人会知道,可以绕过上述要求,让 Windows 11 在官方“不兼容”的硬件上运行。
新处理器指令集中的附加指令?
但是对于该支持列表中的 CPU,它们的指令集中是否有其他指令可供微软开发人员在未来的 Windows 11 版本中使用?
我想知道这些指令是否会出现在 Windows 某些部分的低级汇编代码中,或者是由使用的 C/C++ 编译器在软件的其他地方以机器语言生成的。如果是这种情况,那么在运行 Windows 11 时延长非兼容硬件的使用寿命* 的前景最终会在包含带有这些处理器指令的代码的更新发布后突然结束:没有这些处理器指令的处理器将无法识别它们,并且该软件可能会失败、不可靠或不安全。
如果这些新处理器不引入新的处理器指令,那么现有“不兼容”硬件的前景更加乐观。那么挑战可能仍然是对硬件外围设备(如 TPM 2.0)以及安装环境(如 SecureBoot)的依赖存根。
x86-64 总是 x86-64?
除了 x86 32 位 amd x84-64 或 amd64 64 位指令集(后者仅受 Windows 11 支持)之间的区别之外,我不知道新处理器仅支持任何其他变体。
虚拟化来拯救?
如果兼容处理器中存在这样的附加指令,将来可能会在 Windows 11 中使用,“不兼容”硬件的另一个选项可能是虚拟化层(可能由该行中已建立的第 3 方供应商提供)它将新指令即时转换为旧 CPU 可以支持的指令,而旧 CPU 支持的大多数其他指令只是通过,因此总体性能类似于完全原生的。我们在几个案例中看到了这样的虚拟化和翻译:在 ARM 上的 Windows 上模拟的 x86-64 应用程序,在 M1 上运行的 Apple Rosetta 以支持 Apple Intel 编译的应用程序。
用户体验 - 使虚拟化无缝化,就像机器从启动时就有一个更新的 CPU
对于这种虚拟化制造商来说,确保 Windows 11 在旧硬件上运行的挑战可能是用户体验。理想情况下,它应该在启动后出现,以便 Windows 11 在虚拟化上从启动运行。而不是启动到 Windows 10,然后运行虚拟化应用程序(如 VirtualBox、VMware 或 Parallels 来启动 Windows 11 映像)。那是额外的步骤,笨重,可能不如性能。因此,在我看来,Hypervisor 软件可能是在旧硬件上从一开始就运行 Windows 11 的方法。也欢迎在这里提出想法。
当然,Linux
*在任何人提到它之前,我很清楚 Linux 以及可能仍然在这种“旧”“不兼容”硬件上运行的各种发行版。请注意,因为我每天都使用 Linux,以及 Windows 和 macOS。抱歉,我不是来讨论什么平台比另一个平台更好的概念性讨论。
安装 Ubuntu 时出现错误 0x80370102。
错误
截图 任务管理器
截图 Hyper-V 错误
截图 services.msc
Windows 版本:Microsoft Windows [版本 10.0.19044.1415]
WSL 内核版本:5.10.60.1
的相关输出get-windowsoptionalfeature -online
:
FeatureName : Microsoft-Windows-Subsystem-Linux
State : Enabled
FeatureName : HypervisorPlatform
State : Enabled
FeatureName : VirtualMachinePlatform
State : Enabled
输出bcdedit /v
:
Windows Boot Manager
--------------------
identifier {9dea862c-5cdd-4e70-acc1-f32b344d4795}
device partition=\Device\HarddiskVolume1
path \EFI\Microsoft\Boot\bootmgfw.efi
description Windows Boot Manager
locale en-US
inherit {7ea2e1ac-2e61-4728-aaa3-896d9d0a9f0e}
default {5552da70-e75f-11eb-89e7-b655d79896f6}
resumeobject {5552da6f-e75f-11eb-89e7-b655d79896f6}
displayorder {5552da70-e75f-11eb-89e7-b655d79896f6}
toolsdisplayorder {b2721d73-1db4-4c62-bf78-c548a880142d}
timeout 30
Windows Boot Loader
-------------------
identifier {5552da70-e75f-11eb-89e7-b655d79896f6}
device partition=C:
path \Windows\system32\winload.efi
description Windows 10
locale en-US
inherit {6efb52bf-1766-41db-a6b3-0ee5eff72bd7}
recoverysequence {3b397448-f27e-11eb-9d80-ffe132952db6}
displaymessageoverride Recovery
recoveryenabled Yes
isolatedcontext Yes
allowedinmemorysettings 0x15000075
osdevice partition=C:
systemroot \Windows
resumeobject {5552da6f-e75f-11eb-89e7-b655d79896f6}
nx OptIn
bootmenupolicy Standard
hypervisorlaunchtype Auto
输出coreinfo64
:
Coreinfo v3.52 - Dump information on system CPU and memory topology
Copyright (C) 2008-2021 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz
Intel64 Family 6 Model 78 Stepping 3, GenuineIntel
Microcode signature: 000000CC
HTT * Hyperthreading enabled
CET - Supports Control Flow Enforcement Technology
Kernel CET - Kernel-mode CET Enabled
User CET - User-mode CET Allowed
HYPERVISOR * Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
SGX - Supports Intel SGX
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP * Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX instruction extensions
AVX2 * Supports AVX2 instruction extensions
AVX-512-F - Supports AVX-512 Foundation instructions
AVX-512-DQ - Supports AVX-512 double and quadword instructions
AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF - Supports AVX-512 prefetch instructions
AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD - Supports AVX-512 conflict detection instructions
AVX-512-BW - Supports AVX-512 byte and word instructions
AVX-512-VL - Supports AVX-512 vector length instructions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED * Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX * Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID * Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 00000016 (Basic), 80000008 (Extended).
Maximum implemented address width: 48 bits (virtual), 39 bits (physical).
Processor signature: 000406E3
Logical to Physical Processor Map:
**-- Physical Processor 0 (Hyperthreaded)
--** Physical Processor 1 (Hyperthreaded)
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
**-- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Unified Cache 0, Level 2, 256 KB, Assoc 4, LineSize 64
**** Unified Cache 1, Level 3, 3 MB, Assoc 12, LineSize 64
--** Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Unified Cache 2, Level 2, 256 KB, Assoc 4, LineSize 64
Logical Processor to Group Map:
**** Group 0
ETL:wsl.etl